Assignments
MIT Fall 2024
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Table of Contents
1. Introduction (Intro to SystemVerilog, Simulation with Cocotb, Your FPGA)
- Exercise (SV): Combinational Only Logic I
- Exercise (SV): Combinational Only Logic II
- Exercise (SV): Binary to Seven-Segment
- Exercise (SV): Module Wiring
- Infrastructure: Lab Setup
- Checkoff 01 (FPGA): Repeated Digit Seven-Segment
- Exercise (SV): Sequential Logic
- Exercise (Cocotb): Testing Locally
- Checkoff 02: PWM LED
2. Full, Tunable RGB LED (SPI)
- Checkoff 01 (FPGA): Counting Events
- Checkoff 02 (FPGA): All Eight Seven-Segments
- Exercise (SV and Cocotb): Full SPI Controller
- Checkoff 03 (FPGA): The Whole Thing
3. Sound Effects (UART, Computer Interaction)
- Exercise (SV): Parity
- Exercise (Math): Timing Practice
- Exercise (SV and Cocotb): UART Transmitter
- Checkoff 01 (FPGA): Microphone UART upload
- Exercise (SV and Cocotb): UART Receiver
- Checkoff 02 (FPGA): Audio UART download
4. Pong (HDMI Signaling and Pong)
- Exercise (SV and Cocotb): Video Signal Generation
- Exercise (SV and Cocotb): Transition Minimization
- Exercise (SV and Cocotb): Differential Balancing
- Checkoff 01 (FPGA): Test Patterns
- Checkoff 02 (FPGA): Pong
5. Camera (Device Control with high-speed data)
- Exercise (Math): Clocking
- Exercise (SV+Cocotb): Pixel Reconstructor
- Checkoff 01 (SV+Cocotb+FPGA): PopCat
- Checkoff 02 (FPGA): Camera I
- Checkoff 03 (FPGA): Camera II
6. DDR DRAM Memory (short week)
- Exercise (SV) Cyclic Redundancy Checks
- Checkoff 01 (SV+FPGA) HD Camera
7. Convolution (Signed Numbers and Convolution)
- Exercise: Cyclic Redundancy Checks II
- Checkoffs: Convolution