Clocking

MIT Fall 2024

The questions below are due on Wednesday October 09, 2024; 11:59:00 PM.
 
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With this ring oscillator, I thee wed.

Assuming that each NOT gate has a t_{pd}=35\text{ ps}, answer the following questions:

What will the approximate clock period t_{clk} for the circuit above be? Answer in nanoseconds to within 1% of the correct value.

What will the approximate frequency f_{clk} for the circuit above be? Answer in MHz to within 1% of the correct value.

Refer back to lecture 6. Starting with a 100 MHz clock, calculate a three-tuple of divider, multiplier, divider coefficients to generate 260 MHz. Make sure you keep your intermediate frequencies above 12MHz and below 1.2 GHz.

Enter your answer as a Python list of the three values in order.

You're working at a company designing the jPhone. Consider this part of the system below where:

Registers R1 and R2 have the following timing characteristics:

  • t_{pdR} = 2\text{ ns}
  • t_{cdR} = 1\text{ ns}
  • t_{setup} = 3\text{ ns}
  • t_{hold} = 1\text{ ns}

The combinational logic m9 has:

  • t_{pdm9} = 6\text{ ns}
  • t_{cdm9} = 2\text{ ns}

and:

  • t_{clk} = 15\text{ ns}

A Circuit with some flops and some logic

What is the Setup Slack for this circuit, t_{setupSlack}? Answer in nanoseconds.

What is the Hold Slack for this circuit, t_{holdSlack}? Answer in nanoseconds.

Does this meet timing requirements?

Uhoh it looks like your boss Jeve Stobs is having another one of his "issues" where he starts yelling and demanding things. Yeah the jPhone is revolutionary, but at what cost? Somebody should probably talk to HR about this, but in the meantime, you still have to deal with what he wants. After some redesign, the circuit above has been modified such that it does the next big thing, but you're concerned that this extra delay is going to break the design. Specifically Module m9 has been updated such that it now has:

  • t_{pdm9} = 15\text{ ns}
  • t_{cdm9} = 3\text{ ns}

and you're running the system at:

  • t_{clk} = 8\text{ ns}

Since the system is being pushed so hard, there is now a positive skew of 2\text{ ns} in this system (meaning the clock edge arrives at R2 2 nanoseconds later than it does at R1).

What is the Setup Slack for this circuit, t_{setupSlack}? Answer in nanoseconds.

What is the Hold Slack for this circuit, t_{holdSlack}? Answer in nanoseconds.

Does this meet timing requirements?

Once you're done, camera time is next! Move on to the pixel reconstructor :D.