Timing

Setup and Hold and Everything Else

The questions below are due on Wednesday September 25, 2024; 11:59:00 PM.
 
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Section 1

Consider the circuit below where for module m1:

  • t_{pdl}=9 \text{ ns}
  • t_{cdl}=1 \text{ ns}

And for all registers:

  • t_{pdr}=2 \text{ ns}
  • t_{cdr}=1 \text{ ns}
  • t_{\text{SETUP}}=3 \text{ ns}
  • t_{\text{HOLD}}=2 \text{ ns}

A Circuit with some flops and some logic

What is the t_{SETUP} for the entire circuit above? Answer in nanoseconds.

What is the t_{HOLD} for the entire circuit above? Answer in nanoseconds.

What is the minimum period of the system clock, t_{clk} for the entire circuit above? Answer in nanoseconds.

Section 2

Now consider this circuit where same as before:

  • Module m1:
    • t_{pdl}=9 \text{ ns}
    • t_{cdl}=1 \text{ ns}

And for all registers:

  • t_{pdr}=2 \text{ ns}
  • t_{cdr}=1 \text{ ns}
  • t_{\text{SETUP}}=3 \text{ ns}
  • t_{\text{HOLD}}=2 \text{ ns}

But also for module m0:

  • t_{pdl}=17 \text{ ns}
  • t_{cdl}=3 \text{ ns}

A Circuit with more flops and logic.

What is the t_{SETUP} for the entire circuit above? Answer in nanoseconds.

What is the t_{HOLD} for the entire circuit above? Answer in nanoseconds.

Knowing nothing else about how this circuit is integrated in with other circuits, what is the minimum period of the system clock, t_{clk} for the entire circuit above? Answer in nanoseconds.

Section 3

Consider this new circuit below where:

  • Module m2 (purely combinational):

    • t_{pdl}=13 \text{ ns}
    • t_{cdl}=1 \text{ ns}

  • Module m3 (purely combinational):

    • t_{pdl}=5 \text{ ns}
    • t_{cdl}=3 \text{ ns}

  • And for all registers:

    • t_{pdr}=2 \text{ ns}
    • t_{cdr}=1 \text{ ns}
    • t_{\text{SETUP}}=2 \text{ ns}
    • t_{\text{HOLD}}=2 \text{ ns}

A Circuit with more flops and logic.

If we set a_in to be a constant value that is never changing what is the minimum t_{clk} for this circuit?

What is the minimum period of the system clock, t_{clk} for the entire circuit above? Answer in nanoseconds.

Now consider the case where a_in is free to change:

What is the t_{SETUP} for the entire circuit above (at the input port)? Answer in nanoseconds.

What is the t_{HOLD} for the entire circuit above from (at input port)? Answer in nanoseconds.