Week 06: DRAM
MIT Fall 2024
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More Memory, More Problems
This should be a shorter week, though it does not mean you should start later on it. We'll first get some practice writing a few Linear Feedback Shift Registers, which are a particular family of circuits you'll see in digital circuits a lot for randomization and error correction. Then, for the bulk of this week's content, you'll continue on with your camera work from last week and instead bring in a frame buffer in the DDR DRAM to replace your frame buffer in BRAM. This will require working with a few quite complicated modules that handle the (even more complicated) task of managing the DRAM.
I slightly updated the build.tcl file you should be using for this lab. Use this variant here.
- Exercise (SV) Cyclic Redundancy Checks
- Checkoff 01 (SV+FPGA) HD Camera