Combinational Logic I

Consider the circuit below:

Given the values of I_1, I_2,and I_3 are 0, 0, and 0, enter the values of O_1 and O_2 as a Python list.
(i.e. [O_1, O_2] ).

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Given the values of I_1, I_2,and I_3 are 0, 0, and 1, enter the values of O_1 and O_2 as a Python list.
(i.e. [O_1, O_2] ).

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Given the values of I_1, I_2,and I_3 are 1, 0, and 0, enter the values of O_1 and O_2 as a Python list.
(i.e. [O_1, O_2] ).

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SystemVerilog

SystemVerilog as a language supports¹ all standard logical operations, using C-style syntax, including AND (&&), OR (||), XOR (^) and NOT (!). Consider the very simple digital logic circuit below:

You can write this in two ways in SystemVerilog. The first using an assign statement:

assign c = a && b;

And alternatively as an always_comb. The pros/cons of these two ways will become apparent as you progress in the course.

always_comb begin
  c = a && b;
end

Implement the circuit at the top of the page in SystemVerilog.

module d1( input wire i_1, input wire i_2, input wire i_3, output logic o_1, output logic o_2); // Your code here! endmodule

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Once you're done, move on to the next part of this week's assignments :D