Lectures

Lecture 13 (10/27/2022): Memory

• Slides
• Video

Lecture 12 (10/20/2022): Device-to-Device Communications

• Slides
• Video

Lecture 11 (10/18/2022): Analog in Digital World

• Slides
• Video

Lecture 10 (10/13/2022): AXI Pipelining

• Slides
• Video
  • Project from AXI Audio Demo

Lecture 09 (10/06/2022): Math and Timing

• Slides
• Video
  • Lots of Dividers from Lecture (there's a few edge-case bugs in these...but the idea is right)

Lecture 08 (10/04/2022): Clocks and Timing

• Slides
• Video
  • Divider Project from Lecture

Lecture 07 (9/29/2022): FSMs II and Pipelines I

• Slides
• Video

Lecture 06 (9/27/2022): Finite State Machines

• Slides
• Video
• Divider Module:
  • divider.sv
  • divider_tb.sv

Lecture 05 (9/22/2022): Video Content/Lab 03 Setup

• Slides
• Video
  • Slow-Mo Guys

Lecture 04 (9/20/2022): Sequential Logic Part II

• Slides
• Video
• Code from Beginning Example:
  • File we wrote Live
  • Zipped Up (Entire Project)

Lecture 03 (9/15/2022): Sequential Logic Part I

• Slides
• Video
• Verilog from Ending (Complete)
  • debouncer_1.sv: The debouncer we wrote in class together as friends
  • debouncer_2.sv: An alternate idea written after class with several students
  • debounce_tb.sv: Testbench for these modules

Lecture 02 (9/13/2022): More Combinational Logic and Verilog

• Slides
• Video
• Verilog from Ending (Complete):
  • big_adder.sv: Both flavors of adder showing for loops, parameters,
  • fixed_adder_tb.sv: Testbench for fixed 8-wide 8-bit adder
  • adder_tb.sv: Testbench for parameterizable adder that is flexible in several ways

Lecture 01 (9/08/2022): Intro, Digital Design, Verilog

• Slides
• Handout
• Video