`timescale 1ns / 1ps
`default_nettype none

module debounce_tb;

    //make logics for inputs and outputs!
    logic clk_in;
    logic rst_in;
    logic dirty_in;
    logic clean_out;  //size appropriately!

    //make an instance of the counter...call it uut or my_counter or something else
    debouncer #(.CLK_PERIOD_NS(10),.DEBOUNCE_TIME_MS(0.0001)) uut(  .clk_in(clk_in),
                    .rst_in(rst_in),
                    .dirty_in(dirty_in),
                    .clean_out(clean_out));
    always begin
        #5;  //every 5 ns switch...so period of clock is 10 ns...100 MHz clock
        clk_in = !clk_in;
    end

    //initial block...this is our test simulation
    initial begin
        $dumpfile("debounce.vcd"); //file to store value change dump (vcd)
        $dumpvars(0,debounce_tb); //store everything at the current level and below
        $display("Starting Sim"); //print nice message
        clk_in = 0; //initialize clk (super important)
        rst_in = 0; //initialize rst (super important)
        dirty_in = 0; //initialize evt (super important)
        #20  //wait a little bit of time at beginning
        rst_in = 1; //reset system
        #20; //hold high for a few clock cycles
        rst_in=0;
        #20;
        dirty_in = 1;
        #50
        dirty_in = 0;
        dirty_in = 1;
        #10
        dirty_in = 0;
        #50
        dirty_in = 1;
        #10
        dirty_in = 1;
        #1000
        dirty_in = 0;
        #100
        dirty_in = 1;
        #10
        dirty_in = 0;
        #50
        dirty_in = 1;
        #10
        dirty_in = 0;
        #2000
        dirty_in = 0; //make an evt
        $finish;

    end
endmodule //counter_tb

`default_nettype wire