Information

1) Catalog Description

This class investigates digital design in the context of Field Programmable Gate Arrays (FPGAs), however many of the topics we go over are applicable to the field of digital design as a whole. The class uses the Verilog Hardware Description Language, iVerilog for simulations, and the Vivado/Xilinx/AMD ecosystem for a toolchain and hardware. The primary goal is to actually get in and build something and get it working and to see the good and the bad and the beautiful of hardware design. The first half of the class is devoted to lectures, problem sets, and labs. The latter half of the class is focused on large final projects. There are no exams.

Prerequisites: Starting this year-ish, the prerequisite for class is 6.004. If you don't have it, we'd prefer you be taking it at the same time. If you don't do that, I would prefer you to read some notes from a former 6.004 class (email me for this).

Units: 1-5-6

Lectures: Tuesday, Thursday 2:30-4:00 pm in 32-141. They will be recorded; I make no promise about quality; whatever MIT's auto-capture thing gives us is what we get.

Labs: The lab room is the left (southern) portion of building 38's 6th floor. There are about fifty dedicated computers for working on labs and assignments there, however, we also strongly encourage you to install the appropriate toolchains on your own machine when possible.

Lab Kit: You will be provided a Nexys A7 or Nexys 4DDR board for this class which you must take care of and return. This will be used in all labs and will likely form the center of your final project.

Piazza: The class piazza will be used for all important announcements as well as our official help forum for the class. It is the student's responsibility to make sure to join it and to set their email up so they see these announcements in a timely manner.

Textbook: There are Verilog textbooks out there, but honestly they're all getting outdated. Internet searches and StackOverflow are good starting points for most questions/references. In terms of particular Verilog things:

• This is a good site with System/Verilog basics

2) Staff

Joe Steinmeyer (jodalyst@mit.edu) Instructor 38-583

Jay Lang (jaytlang@mit.edu) TA

Fischer Moseley (fischerm@mit.edu) TA

Alexandra Nwigwe (acnwigwe@mit.edu) LA

Jade Sund (jcsund@mit.edu) LA

Aiden Padilla (aidenfp@mit.edu) LA

3) Grading

Your overall grade is based on the following breakdown:

• Psets: 16%
• Labs: 34%
• Participation: 2%
• Final Project, proposal, revisions, meetings, and final report (the project and keeping on track in it): 48%

A large number of students do "A" level work and are, indeed, rewarded with a grade of "A". The corollary to this is that, since average performance levels are so high, punting any part of the subject can lead to a disappointing grade.

PSets

There will generally be small problem sets that will be released at the end of one lecture and due before the next lectures. Yes, this means that you will sometimes get an assignment on Tuesday and it is due two days later on Thursday. They are not meant to be crazy long, but they exist to force some paced reflection on past material and prep for future material. PSets are done on the website and submitted there. They have a hard deadline (2:29pm, right before lecture on whatever day they are due) and late submissions will not be accepted.

Problem sets collectively are worth 16% of your final grade.

Labs

There are five lab assignments. See the calendar for particular dates of when they are released and when they are due. You work on these assignments in your own time (there is no "lab" sesssion), though feel free to come to office hours, etc. You need to do checkoffs with a staff member to get credit for the lab. This will usually involve demonstrating your simulations, device, and answering questions. Labs are done on your own as are checkoffs. Labs collectively make up 34% of your grade. The breakdown is as follows:

• Lab 1: 3% of final grade
• Lab 2: 5% of final grade
• Lab 3: 8% of final grade
• Lab 4: 10% of final grade
• Lab 5: 8% of final grade

You must have a non-zero score for all labs and all labs must be checked off in order to pass the class. A missing lab will result in a failing grade.

For 2022, labs can be done remotely since you have a kit, however checkoffs must be done in person in lab!

Final Project etc...

Collectively this makes up approximately 48% of your grade. There will be more details as we get closer to final projects.

Exams

There will be no exams in 6.205. You are welcome.

Late Submissions

• Psets are due when they are due. You can’t turn those in late (so don’t skip them!)
• Labs are due at the due date. However they can be turned in late with an increasing point penalty based on lateness. Every day late, they lose 20%. A few additional details on this:
  • Lateness is calculated to the day (minutes and seconds do not come into play). So if lab is due on Thursday at 11:59pm and you do not finish it then, if you turn it in at any point on Friday, it is worth 80%
  • Lateness is applied to each part of the lab individually. For hypothetical Lab N, if you get Checkoffs 1 and 2 done on time, and get Checkoff 3 done one day late, the lateness is only applied to Checkoff 3.
  • Saturday and Sunday do not count in calculation of lateness.

If you feel you need an extension on a lab, email me (jodalyst@mit.edu) >= 48 hours in advance of the lab deadline. Let me know what's going on / how the lab is coming / a general reason why you need some extra time, and as long as you get to me before that 48-hour mark you can generally assume we will grant you a 1 day (24 hour) extension on the lab.

Pro Tip: Turning in assignments late can cause other issues that you don't forsee! If you don't finish Lab 04 until a couple days late, that means Lab 05 is now begun later and you might run into trouble with that. Avoid letting assignments snowball!

If you have any extenuating circumstances that warrant an extension please go to S^3 and then reach out to Joe.

4) Collaboration

To make it short and simple: Labs and PSets should be your own work. You can work together, of course, at a high level, but do not copy someone else's work. Do not email working code to "help" one another. Do not submit somebody else's code. Do not use "your" "friend"'s module because it works and is easier or your tired. Your work should be your own. If we catch you, itwill result in a grade of zero on the assignment, and it will be reported to the Committee on Discipline (COD). Just don't do it.