Documentation

These commands contain the arguments that work in most use cases - every once in a while you'll need to modify them slightly, but these are their most common forms:

• Building a project:
  • With lab-bc: python3 lab-bc.py
  • Locally: vivado -mode batch -source build.tcl
• Flashing the FPGA: openFPGALoader -b arty_a7_100t out.bit
• Simulating a testbench:
  • iverilog -g2012 -o foo.out sim/foo_tb.sv src/foo.sv followed by vvp foo.out
  • Add all the files that iVerilog should be aware of to the command line args. For instance, if your testbench foo_tb makes an instance of foo and foo contains an instance of bar, then you'll need to add the files that contain foo and bar to the command line args.
• Opening GTKWave:
  • Windows/Linux: gtkwave foo.vcd
  • macOS: open foo.vcd
  • Remember that you don't need to close your GTKWave window and reopen it after every simulation! It's way faster to reload the waveform inside your existing window.

• Vivado
• iVerilog
• openFPGAloader/GTKWave
• SSH Key Setup

Full disclosure, some of this is a little jank.

• Camera Board
• DRAM
• Starter Designs (kind of janky)

• How to Debug
• Verilog Style Guide
• Using IP Tastefully