`timescale 1ns / 1ps
`default_nettype none

module divider_tb;

    //make logics for inputs and outputs!
    logic clk_in;
    logic rst_in;
    logic [15:0] dividend_in;
    logic [15:0] divisor_in;
    logic data_valid_in;
    logic [15:0] quotient_out;
    logic [15:0] remainder_out;
    logic error_out, busy_out, data_valid_out;

    divider uut ( .clk_in(clk_in),
                  .rst_in(rst_in),
                  .dividend_in(dividend_in),
                  .divisor_in(divisor_in),
                  .data_valid_in(data_valid_in),
                  .quotient_out(quotient_out),
                  .remainder_out(remainder_out),
                  .data_valid_out(data_valid_out),
                  .error_out(error_out),
                  .busy_out(busy_out));
    always begin
        #5;  //10ns clock period
        clk_in = !clk_in;
    end

    //initial block...this is our test simulation
    initial begin
        $dumpfile("div.vcd"); //dump (vcd)
        $dumpvars(0,divider_tb); //store current level AND below
        $display("Starting Sim"); //print nice message
        clk_in = 0; //initialize clk (super important)
        rst_in = 0; //initialize rst (super important)
        dividend_in = 16'b0;
        divisor_in = 16'b0;
        data_valid_in = 1'b0;
        #20  //wait a little bit of time at beginning
        rst_in = 1; //reset system
        #10; //hold high for a few clock cycles
        rst_in=0;
        #30;
        dividend_in = 16'd1976;
        divisor_in = 16'd23;
        data_valid_in = 1'b1;
        #10;
        data_valid_in = 1'b0;
        #1000;
        divisor_in = 16'b0;
        data_valid_in = 1'b1;
        #10;
        data_valid_in = 1'b0;
        #100;
        $finish;

    end
endmodule //counter_tb

`default_nettype wire