`timescale 1ns / 1ps
`default_nettype none

module big_adder( input wire [7:0] vals_in [7:0],
                        output logic [10:0] sum_out);
  generate
    genvar i;
    for(i =0; i<4; i = i+1)begin: layer1
      logic [8:0] sum;
      assign sum = vals_in[2*i] + vals_in[2*i+1];
    end
    for(i = 0; i<2; i= i+1)begin: layer2
      logic [9:0] sum;
      assign sum = layer1[2*i].sum + layer1[2*i+1].sum;
    end
  endgenerate
  assign sum_out = layer2[0].sum + layer2[1].sum;
endmodule




module big_p_adder #(parameter BUS_WIDTH = 8,
                    parameter COUNT_EXPONENT = 3)
                  ( input wire [BUS_WIDTH-1:0]vals_in [NUM_VALS-1:0],
                    output logic [OUTPUT_WIDTH-1:0] sum_out);
  parameter NUM_VALS = 1<<COUNT_EXPONENT;
  parameter OUTPUT_WIDTH = BUS_WIDTH + COUNT_EXPONENT;
  always_comb begin
    sum_out = 0;
    for(int i = 0; i< NUM_VALS; i = i +1)begin
      sum_out = sum_out + vals_in[i];
    end
  end
endmodule


module small_adder #(parameter BUS_WIDTH_IN = 8)
                   (input wire [BUS_WIDTH_IN -1:0] val_in [1:0],
                    output logic [BUS_WIDTH_IN:0] sum_out);
  assign sum_out = val_in[0] + val_in[1];
endmodule

`default_nettype wire