`timescale 1ns / 1ps
`default_nettype none

module combo_lock #(parameter CODE = 16'hF9AB)
                  ( input wire clk_in, input wire rst_in,
                    input wire val_in,
                    input wire read_in,
                    output logic [15:0] shift_out,
                    output logic buzzer_out);
  logic [4:0] counter;
  logic old_read_in;

  logic read_pulse;

  assign read_pulse = read_in & (~old_read_in);

  always_ff @(posedge clk_in)begin
    old_read_in <= read_in;
  end

  always_ff @(posedge clk_in)begin
    if (rst_in)begin
      shift_out   <= 16'b0;
      buzzer_out  <= 1'b0;
      counter <= 5'b0;
    end else begin
      if(read_pulse && counter < 16)begin
        shift_out <= {shift_out[14:0],val_in};
        counter <= counter +1;
      end else begin
        buzzer_out <= (shift_out == CODE);
      end
    end
  end

endmodule

`default_nettype wire