Documentation

We have three big "parts" of software that we use in 6.205. You need access to all three of them and should go through the installation steps below for each:

• GTKWave/iVerilog: The open-source software we use to simulate and test our digital designs!
• Vivado: The propietary software we use to generate our digital designs!
• openFPGAloader: An open-source cross-platform bit-file flasher which we use to get our designs on our FPGA!

We also have a growing collection of Windows tips.

Quick Command Reference

These commands contain the arguments that work in most use cases - every once in a while you'll need to modify them slightly, but these are their most common forms:

• Building a project:
  • With lab-bc (remote): ./remote/r.py build.py build.tcl {whatever files you need to include}
  • Locally: vivado -mode batch -source build.tcl
• Flashing the FPGA: openFPGALoader -b arty_s7_50 out.bit
• Simulating a testbench:
  • iverilog -g2012 -o foo.out sim/foo_tb.sv src/foo.sv followed by vvp foo.out
  • Add all the files that iVerilog should be aware of to the command line args. For instance, if your testbench foo_tb makes an instance of foo and foo contains an instance of bar, then you'll need to add the files that contain foo and bar to the command line args.
• Opening GTKWave:
  • Windows/Linux: gtkwave foo.vcd
  • macOS: open foo.vcd
  • Remember that you don't need to close your GTKWave window and reopen it after every simulation! It's way faster to reload the waveform inside your existing window.

• 2017 SystemVerilog Standard

• Camera Board software
• DRAM (for reference from the Nexys boards...we are currently working on something for the Urbana board)
• Starter Designs (kind of janky). These were all developed for the Nexys board, but can at least get you started. Reach out Piazza for particular things like some modifications for the SD card)
• How to Debug

• Verilog Style Guide

• Quick notes on how to simulate IP