Lab 01: Checkoff 01 (Seven Segments)

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For a first project, we're going to use the bto7s module you wrote in earlier this week to control the seven-segment display on the Nexys board. It won't control all the digits independently (we'll need sequential logic for that) so each digit on the display will show the same thing. We'll use two .sv files for this: one to contain the bto7s module, and one to connect the module to the physical pins on the chip.

Make both files in the hdl directory of your lab folder.

• Name one bto7s.sv and copy in your working bto7s module from earlier this week into it.
• Make a second file called top_level.sv and transfer the contents below into it:

`timescale 1ns / 1ps
`default_nettype none // prevents system from inferring an undeclared logic (good practice)

module top_level(
  input wire [15:0] sw, //all 16 input slide switches
  input wire [3:0] btn, //all four momentary button switches
  output logic [15:0] led, //16 green output LEDs (located right above switches)
  output logic [2:0] rgb0, //RGB channels of RGB LED0
  output logic [2:0] rgb1, //RGB channels of RGB LED1
  output logic [3:0] ss0_an,//anode control for upper four digits of seven-seg display
  output logic [3:0] ss1_an,//anode control for lower four digits of seven-seg display
  output logic [6:0] ss0_c, //cathode controls for the segments of upper four digits
  output logic [6:0] ss1_c //cathod controls for the segments of lower four digits
  );

  logic [6:0] ss0_cn, ss1_cn; //used for inverting output signal

  // instantiate a bto7s module called 'n1' that controls the upper four 7-seg
  bto7s n1(
      .x_in(sw[7:4]),
      .s_out(ss0_cn)
      );

  // instantiate a bto7s module called 'n0' that controls the lower four 7-seg
  bto7s n0(
      .x_in(sw[3:0]),
      .s_out(ss1_cn)
      );

  assign {ss0_an, ss1_an} = 8'h00; // all low (on). to turn off digits, set high
  assign ss0_c = ~ss0_cn; //the cathodes on the seven segment are active low, so invert
  assign ss1_c = ~ss1_cn; //same as above

  /* we'll use the LEDs later...for now, just link them to the switches
   * and force some lights on
   */

  assign led = sw;
  assign rgb0[0] = 1'b1; //red channel of RGB LED 0
  assign rgb1[2] = 1'b1; //blue channel of RGB LED 1

endmodule // top_level
/* I usually add a comment to associate my endmodule line with the module name
 * this helps when if you have multiple module definitions in a file
 */

// reset the default net type to wire, sometimes other code expects this.
`default_nettype wire

This file is the top level file and its inputs and outputs are actually going to be the pins on the FPGA, which are connected to the peripherals on the development board. Specifically, the module above is dropping the bto7s module into the following sort of schematic (with some little details left out):

The 8 digits of the seven-segment display are actually broken into two banks of four digits each which each share common segment controls. We're going to independently control the upper four digits using sw[7:4] and the lower four digits using sw[3:0]. For this week, we lack the ability to control the individual digits separately (will be done in Week 2), so for now, the value placed on the upper bank of digits will get replicated on all four digits and same with the lower.

The missing "link" is now between our top_level module and the actual FPGA. We've declared an output called led that is 16 bits wide, but the FPGA doesn't know what that physically maps to on the actual chip. The XDC file (top_level.xdc, which you created in lab setup), provides this mapping. We only want to include mappings for connections we actually use, so we'll only uncomment the lines needed to setup the top_level module with its inputs and outputs. XDC files use "#" comments so we just remove the leading # on the necessary lines. Specifially:

For example to activate sw[0] you'd simply start with this:

## USER SLIDE SWITCH
#set_property -dict {PACKAGE_PIN G1  IOSTANDARD LVCMOS33} [ get_ports "sw[0]" ]
#set_property -dict {PACKAGE_PIN F2  IOSTANDARD LVCMOS33} [ get_ports "sw[1]" ]
#set_property -dict {PACKAGE_PIN F1  IOSTANDARD LVCMOS33} [ get_ports "sw[2]" ]

and then go to this:

## USER SLIDE SWITCH
set_property -dict {PACKAGE_PIN G1  IOSTANDARD LVCMOS33} [ get_ports "sw[0]" ]
#set_property -dict {PACKAGE_PIN F2  IOSTANDARD LVCMOS33} [ get_ports "sw[1]" ]
#set_property -dict {PACKAGE_PIN F1  IOSTANDARD LVCMOS33} [ get_ports "sw[2]" ]

For our designs in this lab, we want to use the following connections on the chip:

• All 16 sw pins. (active high)
• The four btn buttons (even though we'll only use three). (active high)
• All 16 led pins (active high)
• All 8 an anode pins of the seven-segment display, which are split into two "banks":
  • ss0_an[3:0] which control the on/off nature of each of the four upper digits (active low)
  • ss1_an[3:0] which controls the on/off nature of each of the four lower digits (active low)
• The cathode pins of the seven-segment display, which are split into two "banks":
  • ss0_c[6:0] which controls the segments of all four upper digits (active low)
  • ss1_c[6:0] which controls the segments of all four lower digits (active low)
• The two RGB LEDs on the board. While we'll only use the red and blue channel of two different ones, we'll bring in both LEDs fully:
  • rgb0[2:0] which is the blue, green, and red controls (active high) for the left RGB LED
  • rgb1[2:0] which is the blue, green, and red controls (active high) for the right RGB LED

Build

Using your preferred Vivado setup, generate a bitstream for this design:

• If you are running Vivado locally (your own machine or a lab machine), do vivado -mode batch -source build.tcl, and watch the messages scroll by. -mode batch forces Vivado to build on the command line, and -source build.tcl forces Vivado to use your build script rather than defaulting to a 'project-mode' setup. Here is a copy of a pretty generic build.tcl that you should put in the root of your lab folder. Both of these save you a ton of time - get used to using them! If all goes well, this should succeed, and you'll wind up with an output file in obj.

• If you're using lab-bc, things have to be a little more verbose. Assuming you set up your project file as we stated in the Lab setup page, you should run: ./remote/r.py build.py build.tcl hdl/top_level.sv hdl/bto7s.sv xdc/top_level.xdc obj/ and essentially the same thing should happen, and you'll also wind up with a build log in obj and output bit file there too!

Once this is done, using openFPGALoader, flash the output bitfile (obj/final.bit) to your FPGA. Verify that the lower four bits can set all sixteen appropriate digits on the displays like shown in the video below.

If things don't work, scroll through the readout Vivado gives you! Look for ERROR, since that is likely an error. The output vivado.log is a text file and completely searchable as well in case you don't want to scroll through all the readout manually!

Checkoff 1:
For checkoff 1, show your seven segment display working with the lower four switches.

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Once you're done, continue onto making a super cool ALU in Checkoff 02 :D