Assignments
MIT Fall 2026
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Table of Contents
1. Introduction (Intro to SystemVerilog, Simulation with Cocotb, Your FPGA)
- Exercise (SV): Combinational Logic I
- Exercise (SV): Combinational Logic II
- Exercise (SV): Binary-to-Seven-Segment
- Exercise (SV): Module Wiring
- Infrastructure: Lab Setup
- Checkoff 01 (FPGA): Repeated Digit Seven-Segment
- Exercise (SV): Sequential Logic
- Checkoff 02 (Cocotb): Testing Locally
- Checkoff 03: PWM LED