Assignments

MIT Fall 2026

You are not logged in.
Please Log In for full access to the web site.
Note that this link will take you to an external site (https://shimmer.mit.edu) to authenticate, and then you will be redirected back to this page.

Table of Contents

1. Introduction (Intro to SystemVerilog, Simulation with Cocotb, Your FPGA)

Exercise (SV): Combinational Logic I
Exercise (SV): Combinational Logic II
Exercise (SV): Binary-to-Seven-Segment
Exercise (SV): Module Wiring
Infrastructure: Lab Setup
Checkoff 01 (FPGA): Repeated Digit Seven-Segment
Exercise (SV): Sequential Logic
Checkoff 02 (Cocotb): Testing Locally
Checkoff 03: PWM LED

2. Full, Tunable RGB LED (SPI)

Checkoff 01 (FPGA): Counting Events
Checkoff 02 (FPGA): All Eight Seven-Segments
Exercise (SV and Cocotb): Full SPI Controller
Checkoff 03 (FPGA): The Whole Thing

3. Sound Effects (UART, Computer Interaction)

Exercise (Math): Timing Practice
Exercise (SV and Cocotb): UART Transmitter
Checkoff 01 (FPGA): Microphone UART upload
Exercise (SV and Cocotb): UART Receiver
Checkoff 02 (FPGA): Audio UART download
Exercise (SV) and Checkoff 03: Parity

4. Pong (HDMI Signaling and Pong)

Exercise (SV): Timing
Exercise (SV): Linear Feedback Shift Registers
Exercise (SV and Cocotb): Video Signal Generation
Exercise (SV and Cocotb): Transition Minimization
Exercise (SV and Cocotb): Differential Balancing
Checkoff 01 (FPGA): Test Patterns
Checkoff 02 (FPGA): Pong