Combinational Logic

Consider the circuit below:

Given the values of I_1, I_2,and I_3 are 1, 0, and 1, enter the values of O_1 and O_2 as a Python list.
(i.e. [O_1, O_2] ).

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Given the values of I_1, I_2,and I_3 are 0, 1, and 0, enter the values of O_1 and O_2 as a Python list.
(i.e. [O_1, O_2] ).

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Given the values of I_1, I_2,and I_3 are 1, 1, and 1, enter the values of O_1 and O_2 as a Python list.
(i.e. [O_1, O_2] ).

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Implement the circuit above in SystemVerilog.

module d1( input wire i_1, input wire i_2, input wire i_3, output logic o_1, output logic o_2); // Your code here! endmodule

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Assume the following about the contamination delay t_{cd} and propagation delay t_{pd} of the above logic gates:

• AND Gate: t_{cd}=50\text{ ps}, t_{pd}=60\text{ ps}
• OR Gate: t_{cd}=45\text{ ps}, t_{pd}=65\text{ ps}
• XOR Gate: t_{cd}=65\text{ ps}, t_{pd}=85\text{ ps}

Remember, t_{cd} is the minimum guaranteed time that the circuit will NOT change its output given a change to any of its inputs. t_{pd} is the maximum potential time before the output of a circuit will change given a change to any of its inputs.

What is the t_{cd} of the entire circuit? Answer in picoseconds.

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What is the t_{pd} of the entire circuit? Answer in picoseconds.

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Given the results above, how many times per second can this circuit accept a new set of inputs and provide an output? Hint: One second is 10^{12} \text{ ps} .

How many times per second can this circuit process a unique input?

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