`default_nettype none
`timescale 1ns/1ps


//ADDER parameterized to use in BUS_WIDTH_IN to specify width of two
//inputs and then calculate (combinationally) their sum (with sufficient bits)
//input vals_in
//output sum_out

module adder #( parameter BUS_WIDTH_IN = 8)
            ( input wire [BUS_WIDTH_IN -1 :0] val_in [1:0],
              output logic [BUS_WIDTH_OUT-1:0] sum_out);
  localparam BUS_WIDTH_OUT = BUS_WIDTH_IN + 1;
  always_comb begin
    sum_out = val_in[0] + val_in[1];
  end
endmodule //adder

//ADDER parameterized to use in BUS_WIDTH_IN to specify width of NUM_VALS inputs
//and then calculate (combinationally) their sum (with sufficient bits)
//input vals_in
//output sum_out

module p_adder #( parameter BUS_WIDTH_IN = 8,
                  parameter NUM_VALS = 8)

          (     input wire [BUS_WIDTH_IN-1:0] vals_in [NUM_VALS-1:0],
                output logic [BUS_WIDTH_OUT-1:0] sum_out);
      localparam BUS_WIDTH_OUT = BUS_WIDTH_IN + $clog2(NUM_VALS);
  always_comb begin
    sum_out = 0;
    for (int i = 0; i< NUM_VALS; i = i +1)begin
      sum_out = sum_out + vals_in[i];
    end
  end
endmodule //p_adder


//ADDER with EIGHT (8) 8-bit inputs. Sums them up in a tree structure
//routes to output:
//input vals_in
//output sum_out
//could also make this paremeterized and with some  nested for loops
// get a variable-depth tree structure.
// note on this design...chances are very good that any reasonable
// compiler/toolchain would infer a tree structure even if you gave it a
// thing like sum_out = vals_in[0] + vals_in[1] + vals_in[2]+...
// (like the previous example)

module big_adder (input wire [7:0] vals_in [7:0],
                  output logic [10:0] sum_out);
  generate
    genvar i;
    for (i = 0; i<4; i=i+1)begin: layer1
      logic [8:0] sum;
      assign sum = vals_in[2*i] + vals_in[2*i+1];
    end
    for (i = 0; i<2; i=i+1)begin: layer2
      logic [9:0] sum;
      assign sum = layer1[2*i].sum + layer1[2*i+1].sum;
    end
  endgenerate
  assign sum_out = layer2[0].sum + layer2[1].sum;
endmodule



`default_nettype wire